In recent years, III-V nitride compound semiconductors have been mainly used in blue LEDs and blue-violet semiconductor lasers. III-V nitride compound semiconductors are grown on an ordinary sapphire substrate or SiC substrate using MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), or another crystal growth method because it is difficult to obtain a low-defect GaN substrate or another III-V nitride compound semiconductor substrate.
The difference in the lattice constants between the sapphire substrate and the GaN-based semiconductor layer is considerable in a nitride-based semiconductor element composed of a GaN-based compound semiconductor layer on a sapphire substrate, for example. For this reason, the GaN-based semiconductor layer formed on a sapphire substrate contains a large number of dislocations, and the crystallinity is reduced. It is therefore difficult to achieve good element characteristics in a III-V nitride compound semiconductor element in which a sapphire substrate or the like is used. There is therefore a need for a substrate of the same quality as a GaN substrate that has few crystal defects in order to manufacture a III-V nitride compound semiconductor element.
A method of manufacturing a single-crystal GaN substrate is disclosed in Patent Document 1 noted below as a III-V nitride compound semiconductor substrate that solves such problems, wherein the growth surface of vapor phase growth is endowed with a 3-D facet structure, and dislocations are reduced by growing the crystal so that the facet structure is not embedded. This method of manufacturing a GaN substrate reduces threading dislocations in other locations by concentrating the threading dislocations in a region in the grown layer. Therefore, low density dislocation regions and high density dislocation sections are both present in the single-crystal GaN substrate. In particular, high density dislocation sections occur at random, and the position where these sections occur cannot be controlled. Accordingly, the formation of high density dislocation sections in light emitting regions cannot be avoided, and there is therefore a problem in that the reliability and light emitting characteristics of a nitride semiconductor light emitting element are liable to be compromised.
On the other hand, the invention of a method of manufacturing a III-V nitride compound semiconductor substrate is disclosed in Patent Document 2 noted below as a solution to the problems of the invention of a method of manufacturing a III-V nitride compound semiconductor substrate disclosed in Patent Document 1, wherein the position of the high density dislocation sections generated in the low density dislocation regions is controlled, a substrate in which the high density dislocation sections are regularly, e.g., periodically arranged in the low density dislocation regions can be obtained, and an arrangement pattern of high density dislocation sections can be freely modified. The method of manufacturing a III-V nitride compound semiconductor substrate disclosed in Patent Document 2 noted below is one in which a crystal is grown having an inclined surface composed of a facet plane in the same manner as the invention disclosed in Patent Document 1 noted below, and dislocations are propagated and made to concentrate in prescribed positions by maintaining and growing the inclined surface composed of the facet plane.
Following is a specific method of manufacturing a GaN substrate 50 as a III-V nitride compound semiconductor substrate disclosed in Patent Document 2. First, a seed composed of, e.g., an SiO2 film is formed on a base substrate using a sapphire substrate, a GaN substrate, or another base substrate. The seed is formed in an arrangement that corresponds to the arrangement of dotted high density dislocation sections B, such as the dotted configuration shown in FIG. 5 or 6, for example, or an arrangement that corresponds to the arrangement of striped high density dislocation sections B shown in FIG. 7. A thick film of GaN is then grown by hydride vapor phase epitaxy (HVPE), for example. A facet plane that corresponds to the pattern shape of the seed is formed on the surface of the GaN thick film layer after growth. Pits composed of facet planes such as those shown in FIG. 5 or 6 are regularly formed when the seed has a dotted pattern. On the other hand, a prism facet plane such as that shown in FIG. 7 is formed when the seed has a striped pattern. The base substrate is then removed and the GaN thick film layer is ground and polished to flatten the surface. The GaN substrate 50 can thereby be manufactured.
A GaN substrate 50 manufactured in this manner is a substrate in which the C plane is the main surface, the dotted or striped high density dislocation sections B having a prescribed size are regularly formed, and the single-crystal regions other than the high density dislocation sections B, i.e., regions A, have a lower dislocation density than the high density dislocation sections B. In view of this fact, it is possible to dispose the element regions in an arrangement in which the effect of the high density dislocation sections B that have a large number of defects can be intentionally avoided using the GaN substrate 50 by adopting the following.
(1) The size of the element is designed to conform to the period in which the high density dislocation sections B are present;
(2) the arrangement of element regions on the substrate is determined so that the element regions are essentially not formed in the high density dislocation sections B; and
(3) the positions of the active regions in the element are designed so that the active regions inside the element are not formed in the high density dislocation sections B.
In addition, in the particular case of a semiconductor laser element, the element regions and the element structures are designed so that the end face of a resonator of a light emitting area is not formed in the high density dislocation sections B. For example, element regions 52 (sections enclosed by a thick solid line) are demarcated in a shape and arrangement such as those shown in FIGS. 8A to 8D, and a laser stripe 53 is demarcated adjacent to the center when the striped high density dislocation sections B are formed in the manner shown in FIG. 7.
A GaN-based semiconductor layer that forms a laser structure is grown on the GaN substrate 60; laser stripe formation, electrode formation, and other required processes are carried out to form a laser structure; and the GaN substrate 50 on which the laser structure is formed is thereafter scribed along the contour lines of the element regions 52 described above, whereby individual GaN-based semiconductor laser chips are separated. In this case, the effect of the high density dislocation sections B can be prevented from extending to the light emitting regions because the high density dislocation sections B are not formed on the laser stripe 53. Therefore, a highly reliable GaN-based semiconductor laser element having good light emitting characteristics can be obtained.
Disclosed in Patent Document 3 noted below is a method of manufacturing a III-V nitride compound semiconductor light emitting element in which light emitting element regions are formed so that stripe-shaped light emitting regions are made parallel to the direction in which the high density dislocation sections extend in the low density dislocation regions on the III-V nitride compound semiconductor substrate in which the high density dislocation sections are repeatedly arranged while alternating with the low density dislocation regions, two scribe lines are subsequently formed in positions of about 10 μm from the center line between adjacent elements on a surface on which the light emitting element regions are formed, and the substrate is then broken apart, whereby chip separation is performed and the high density dislocation sections are removed.
[Patent Reference 1]: Japanese Laid-open Patent Application No. 2001-102307
[Patent Reference 2]: Japanese Laid-open Patent Application No. 2003-124572 (Claims, paragraph nos. 0231 to 0256, 0274 to 0289, FIGS. 6 to 8, and FIGS. 23 to 36)
[Patent Reference 3]: Japanese Laid-open Patent Application No. 2004-260152 (Paragraph nos. 0065 to 0070, and FIGS. 13 to 14)